|
Design a divide by 3, 50% duty cycle counter. Input clock is of 100KHz,
o/p clock should be of 33KHz,
50% duty cycle.
Design a counter to give Divide by 60, 50% duty cycle clock.
Design a circuit to give 2/3 of the clock
frequency.
Design an RS-232 transmitter with the following specification
The IC contains an 8 bit parallel data when
valid is high. It converts
the parallel data into serial data, and sends the serial data on the
data_out line.
The data out line remains high when it is idle.
On the data out line first a low start bit is transmitter, then the
serial
data bit (LSB First) then a high stop bit.While the data is
being transmitted, the hold output remains high. The device
that is
writing data should not write the next byte as long as hold is high.
The serial data is transmitted one bit
per clock.
Design a keyboard scanner. It will scan a matrix of 4*4 keys and give
out a four bit binary code of
the key pressed. Also it will assert a
signal “VALID” when a key is pressed.
Design a protocol for
communication system consisting of a transmitter
and a receiver. The data packet consists of a stream of bytes
transferred
parallel over 8 lines. Both the control and data byte are
transferred over the same lines. The length of the packet
is variable.
Define a suitable packet structure. Flow control should be possible.
Some error detection mechanism should
be incorporated.
Assume that the data transfer is half duplex. Assume that both the transmitter
and receiver use the
same clock.
Design a 3*3 crossbar switch. The data path for each port is 8 bit wide.
In addition to the data
line each input port has the following control signals
associated with it.
1. Request
2. Grant
3. Destination port ID (2 bit).
The device sending
data to a particular port of the crossbar has
to first give a “destination port ID”, then give a request.
The
crossbar will check whether the destination port is free, and if it
is free a ‘grant’ will be
given.Once a grant is given. Once the grant
is given the crossbar will connect the input port to the requested
output
port. The request has to be kept high as long as the data is
being transmitted. The circuit has to be a synchronous
circuit. The
switch has to be non blocking.
Design a circuit for a rotation sensor which not only tells you the
RPM
Design
an FSM that accepts all strings over 0 and 1 such that the last three bits have
at least two 1’s. You should not
use more than 4 states.
Design an FSM that does a 2/3 of the input frequency. If the i/p is 100MHz the
o/p should be 66MHz.
Design
a circuit to detect a sequence of 32 1’s and 0’s and produce an output 1 if this
sequence
is detected. If this sequence breaks at any moment the it should return to its
initial state and again start checking
for the bit stream. ( used in ATM).
Design a circuit for a traffic light control for a four way with Yellow light for 4
s and Green
light for 32 s. The input clock frequency is 1.048576 MHz.
Design a DRAM Controller for the following
specifications.
1. Use CAS before RAS refresh method.
2.
Refresh counter is built inside the DRAM.
3. Memory access to the CPU is provided via the
Controller.
4. Refresh should be given priority over read write.
5. The controller has to be interfaced with 68000 micro processor.
6. Page refresh
has to be provided.
|
